Real-time implementation of fast discriminative scale space tracking algorithm

Abstract Real-time object tracking is an important step of many modern image processing applications. The efficient hardware design real-time tracker must achieve the desired accuracy while satisfying frame rate requirements for a variety sizes. existing methods visual employ sophisticated algorithms and challenge capabilities most embedded architectures. Discriminative scale space one algorithm that capable demonstrating good performance with affordable complexity. It has high degree parallelism which can be exploited implementation reconfigurable This paper proposes discriminative scale-space on FPGA major blocks. A careful exploration core mathematical operations performed to improve their utilization timing performance. Among functional units optimized in this work, discrete Fourier transform achieves computational time improvement 92% relative works, QR factorization 2.3 $$\times$$ × reduction resource utilization, singular value decomposition yields 3.8 time. proposed data path architecture designed using Vivado HLS tool set implemented Zync Zed Board (xc7z020clg484-1). For input size 320 240, mean 25.38 fps.